Senior Hardware Security Engineer

Microsoft’s Systems Planning and Architecture (SPARC) team within Azure Hardware Systems and Infrastructure (AHSI) builds the cloud infrastructure that powers Microsoft’s Intelligent Cloud mission. As a Senior Hardware Security Engineer in Redmond, WA (onsite), you’ll help shape security infrastructure for AI technologies and platform components across the full product lifecycle, from threat modeling and secure silicon design through manufacturing, supply chain, and high-scale deployment.

This role supports security architecture for core AI technologies (including accelerator modules such as MAIA) and helps ensure platform components can meet throughput and latency expectations. You’ll partner with security and platform infrastructure teams as designs move from silicon to platform management.

What you’ll do

• Architect security infrastructure around core AI technologies so platform components work together effectively with throughput and latency requirements.
• Develop AI agents to support security analysis of code and architecture.
• Perform threat model analysis for platform components and their interactions across the system.
• Work from open-ended problem statements by translating business requirements and fleet telemetry into clear technical problem definitions.
• Own infrastructure management architecture during the design phase, guiding solutions from silicon through platform.
• Collaborate across multiple phases of product development as priorities shift through architecture, design, and validation.

What you’ll bring

• Master’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or a related field AND 3+ years of technical engineering experience, OR Bachelor’s Degree in a related field AND 5+ years of technical engineering experience, OR equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including completion of the Microsoft Cloud Background Check (required to pass upon hire/transfer and every two years thereafter).
• 10+ years of professional experience spanning architecture, design, and validation of SOC internal blocks for SOCs such as CPU, GPU, or networking devices.
• Demonstrable skills in System Verilog, synthesis tools, pre-silicon timing path debug and fixes, UVM, and C and Python; Rust knowledge is a plus.
• Familiarity with PCIe architecture and server architectures is a strong advantage.
• Ability to debug and resolve issues that span multiple subsystems.
• Comfort learning newer areas and operating across architecture, design, and validation with a flexible, multi-hat approach.
• Strong problem solving, debugging, and troubleshooting skills, plus advanced design and development capability.

Technologies you’ll work with

• System Verilog, Synthesis tools, UVM
• C, Python
• Rust (good to have)
• PCIe

Compensation

Salary range: USD 119,800 - 261,000 per year. The typical base pay range across the U.S. is USD $119,800 - $234,700. Base pay ranges vary by location, including San Francisco Bay area and New York City metro area where the range is USD $160,200 - $261,000. Certain roles may be eligible for benefits and other compensation. Additional pay information is available at: https://careers.microsoft.com/us/en/us-corporate-pay.